La-9413p Rev 1.0 Schematic __link__ [SECURE ✔]

LA-9413P Rev 1.0 Schematic — Informative Post

Page 1 (Block Diagram)

Not always present, but if available, this shows major chip interconnects: CPU ↔ PCH ↔ EC ↔ Power.

Key Sections in the Schematic

• Power & Charging: AC input, DC jack, battery connector, charging controller, PMIC and power rail distribution (3.3V, 5V, VCORE, VCCIO).
• CPU/Chipset: CPU socket or BGA pinouts, chipset power sequencing, clock sources, thermal sensors.
• Memory: DDR lanes, termination resistors, memory power rails, SPD EEPROM.
• Display Subsystem: eDP/LVDS connector, display power, backlight inverter or LED driver.
• Storage & I/O: SATA/PCIe lanes, M.2 slots, USB ports, audio codec connections.
• Embedded Controllers: EC/BIOS circuits, SPI flash for firmware, CMOS battery.
• Networking: Wi‑Fi/Bluetooth module connector, antenna routing.
• Protection & Filtering: Fuses (polyfuse), TVS diodes, EMI capacitors and common-mode chokes on USB and power lines.
• Test Points & Debug: Test pads for voltages, I2C/SMBus lines, JTAG/serial headers (if present).

1. No power, no LED

• Check DC-in mosfets (PQ301/PQ302) – shorted or open.
• Measure +CHG_REG (typically 19V->5V/3.3V standby regulator).
• Replace PU301 (BQ24737) if no ACDET or ACOK.