Desktop Motherboard Power Sequence Pdf -
Understanding the desktop motherboard power sequence is like following a complex relay race. Before your computer even shows a logo, a specific chain of electrical handshakes must occur in a precise order. If just one signal fails, the board remains "dead" or stuck in a boot loop. 1. The Standby Phase (S5 State)
Before you even touch the power button, the Power Supply Unit (PSU) is already talking to the motherboard.
5VSB (5V Standby): The moment you plug in the PSU, it sends 5 volts to the Super I/O (SIO) chip and the Southbridge/PCH.
RTC & Crystal: The CMOS battery powers the Real-Time Clock (RTC), and the crystal oscillator starts vibrating at a specific frequency (usually 32.768 KHz) to keep the system's heartbeat steady.
RSMRST# (Resume Reset): The SIO chip sends this 3.3V signal to the Southbridge to tell it that the standby power is stable and it's ready to wake up. 2. The Trigger: Pressing the Power Button
This is where the physical action translates into a digital command.
PSIN / PWRBTN#: Pressing the button sends a signal to the SIO chip. The SIO then relays this as a PSOUT or PWRON# signal to the Southbridge. desktop motherboard power sequence pdf
The Wake-Up Call (SLP_S3/S4): The Southbridge responds by releasing "Sleep" signals—SLP_S4 and SLP_S3—which travel back to the SIO, signaling it to fully power on the system. 3. Full Power-On (S0 State)
Once the SIO gets the green light from the Southbridge, it triggers the PSU to provide main power.
PSON#: The SIO pulls the green wire on the 24-pin ATX connector to 0V (Ground). This tells the PSU to dump the main 3.3V, 5V, and 12V rails into the motherboard.
Voltage Regulation: These raw voltages are converted by local regulators into specialized power for components like RAM (1.2V–1.5V) and the Chipset (1.05V). 4. The CPU and VRM Handshake
The CPU is the last "major" component to get power because it requires the most precision.
VRM Activation: The Voltage Regulator Module (VRM) receives 12V and waits for an "Enable" signal. Once active, it generates VCORE (the CPU's main power). Understanding the desktop motherboard power sequence is like
Power Good (PWROK): When all voltages (RAM, Chipset, CPU) are stable, a Power Good signal is sent back to the Southbridge/PCH. 5. Reset and BIOS Execution
The final steps prepare the hardware to actually run software.
PLTRST# (Platform Reset): The Southbridge releases the Reset signal to the SIO, Northbridge, and other peripherals.
CPURST#: Finally, the Northbridge/PCH sends a Reset signal to the CPU itself, telling it to start executing the first line of code from the BIOS/UEFI chip.
POST: The BIOS begins the Power-On Self-Test, checking the RAM and GPU before finally handing control to your Operating System. Troubleshooting Guide for a "Dead" Board
If your board won't turn on, technicians typically check these points in order: Check 5VSB: Is the SIO getting standby power? Stage 5: Chipset Core Power (VCC Core)
Verify RSMRST#: Is the SIO telling the Southbridge that power is okay?
Monitor SLP_S3/S4: If these don't trigger when you press the button, the Southbridge/PCH may be faulty.
Test PSON: Does the green wire on the PSU drop to 0V when you hit the button? If not, the SIO isn't telling the PSU to start.
You can find more detailed visual diagrams in resources like the Desktop Motherboard Power Sequence Guide on Scribd or technical PDFs from manufacturers like ASRock and ROHM Semiconductor. Desktop Motherboard Power Sequence Explained - Scribd
Stage 5: Chipset Core Power (VCC Core)
- The PCH (Platform Controller Hub) receives its main core voltage, typically 1.05V (for modern Intel) or 1.8V/1.0V (AMD).
- Once stable, the PCH releases RSMRST# (Resume Well Reset) – a key signal indicating standby power is OK.
Stage 0: AC Power Applied (Standby)
- The power supply is plugged in and switched on.
- +5VSB (Standby Voltage) is generated by the PSU and sent to the motherboard.
- This powers the Real-Time Clock (RTC), CMOS memory, and the Super I/O chip.
- The 3VSB rail is created onboard (from 5VSB) to power the southbridge/PCH’s standby logic.
Part 4: How to Read a Power Sequence Timing Diagram (PDF Example)
Let’s simulate a typical PDF page. You see a horizontal timeline with labels:
+5VSB |--------------------| (always on)
PS_ON# |____________________| (low pulse)
+12V | |--------|
PWR_OK | |-----|
VDD_SPD | |---|
DRAM_VDD | |--|
VCORE_EN | |--|
VCORE | |-|
VRM_GD | |-|
PLTRST# | |---|
Interpretation:
- PS_ON# goes low → +12V rises after 50ms.
- PWR_OK rises 200ms after +12V stable.
- Only after PWR_OK does memory power turn on.
- VCORE begins after VCORE_EN and ramps over 5ms.
- Platform reset is the last to de-assert.
If you measure with an oscilloscope and see PLTRST# going high before VCORE is stable, the board will never boot.
9. References
- Intel Platform Design Guide (NDA, but summaries exist)
- AMD PPR (Processor Programming Reference) – public sections
- ATX Specification v3.0 (free on sffcommittee.org)
- Vendor schematics (Gigabyte, ASUS – limited public)